1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an embedded dynamic random access memory (DRAM).
2. Description of the Related Art
To meet the requirement of higher and higher integration, an integrated circuit is designed with a smaller and smaller dimension. A single DRAM cell comprising a MOS transistor and a capacitor. Therefore, in an integrated circuit comprising a DRAM, a smaller dimension is obtained by reducing the size of a transistor and a capacitor, or saving the space occupied by an interconnect between devices. By decreasing the dimension of a capacitor, the surface area is reduced, and therefore, the resistance effect becomes more obvious, and the quality of capacitor is degraded. Being restricted by the technique limit, a degradation occurs while further reducing the dimension of the transistor. Thus, in an embedded DRAM, a buried-in bit line is formed to save the space occupied by interconnects. Consequently, the dimension of the integrated circuit is reduced.
In a conventional integrated circuit comprising embedded DRAMs, various levels and types of contacts, for example, contacts for bit lines, contacts for capacitors, and contacts for logic circuits, are formed in different process, respectively. In each process of forming a contact, a metal layer, such as a tungsten layer, is formed and etched back or processed by chemical-mechanical polishing (CMP). After the formation of a contact, another metal layer is formed for electrical connection. The process is very complex, and the cost of fabrication is high.